Buffer, buffer operation and method of manufacture
US6784470B2 · kind B2 · utility
15Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 6, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Mar 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/567
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.