Power distribution plane layout for VLSI packages
US6784531B2 · kind B2 · utility
4Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Dec 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49169
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hexagonal conductor path layout for power and ground distribution planes in a multi-layer VLSI device. The invention reduces crosstalk between switching devices in signal nets by reducing impedance in the distribution planes. Impedance is reduced by providing more direct line current paths and providing maximum path change angles of less than ninety degrees. Reduced impedance causes reduced coupling between current flows which share a common path and hence less crosstalk.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.