I/O buffer having a protection circuit for handling different voltage supply levels
US6784693B2 · kind B2 · utility
5Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Apr 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An I/O buffer circuit is disclosed which includes protection circuitry to allow the I/O buffer circuit to tolerate multiple voltages. Further, the buffer circuit is adapted to have little to no leakage current. The buffer circuit includes an output portion that consists of a PMOS transistor in series with two NMOS transistors. Further, the PMOS transistor is controlled by a protection circuit that is operative to prevent leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.