Multistage pulse width modulator
US6784710B2 · kind B2 · utility
3Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two or more pulse width modulation stages, each having progressively higher resolution, are utilized to allow the lower resolution stage or stages to operate at lower clock speeds. Later stages are operated at higher clock speeds and thus a smaller portion of the total pulse width modulation circuit utilizes the higher clock speed. Additionally, later stages operate over smaller time intervals in order to reduce usage of the later stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.