Amplifier circuit
US6784747B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/211
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit and fabrication method including a bias input node, an RF input node, an RF output node, and a plurality of amplifier cells. Each cell has a plurality of discrete emitter contacts of a first conductivity type, a plurality of discrete base contacts of a second conductivity type and grouped in two or more groups, at least one collector contact of the first conductivity type connected to the RF output node, and a base capacitor for each group having two electrodes: an input electrode coupled to the RF input node and an output electrode coupled to a group of discrete base contacts. There is also a base resistor for each group having an input coupled to the bias input node and an output coupled to a group of discrete base contacts. An emitter resistor is coupled to each discrete emitter contact to provide more effective base ballasting and thermal stability than with a cascode arrangement of HBT transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.