Method and apparatus providing resampling function in a modulus prescaler of a frequency source
US6784751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.