Power sequence protection for a level shifter
US6785107B1 · kind B1 · utility
10Cited by
15References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.