Method and apparatus for improving noise immunity in a DDR SDRAM system
US6785189B2 · kind B2 · utility
50Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory controller for use with a DDR SDRAM, an apparatus improves the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method adjusts the noise immunity provided by the apparatus. In particular DQS quality circuits frame the DQS signal for a predetermined portion of the READ operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.