Apparatus and method of performing addition and rounding operation in parallel for floating-point arithmetic logical unit
US6785701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2001 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Oct 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.