System and method for sharing I/O address translation caching across multiple host bridges
US6785759B1 · kind B1 · utility
14Cited by
17References
23Claims
0Family size
Assignee
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Key dates
| Filing date | May 10, 2000 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.