Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
US6785775B1 · kind B1 · utility
2Cited by
16References
25Claims
0Family size
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Key dates
| Filing date | Mar 19, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Dec 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.