Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor
US6785802B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Jan 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and associated method includes a plurality of resources for executing instructions, and an out-of-order instruction shelf for priority/age tracking of the instructions. The instruction shelf has an instruction pool with a plurality of slots therein for storing respective instructions, and an instruction age tracker for storing therein a matrix of rows and columns of logic states associated with relative ages of instructions. The logic states in a given column and row of the matrix are associated with a respective slot of the instruction pool. Also, the microprocessor includes an instructions scheduler for performing at least one logic function on each column of the matrix to determine an oldest instruction, for dispatching instructions to the plurality of resources based thereon, and for updating the matrix based upon dispatched instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.