Method and apparatus for generating parity-check bits from a symbol set
US6785863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention encompasses a method for determining values for parity check bits (p1, . . . , pm) based on a current symbol set (s1, . . . , sk). The method comprises the steps of receiving the current symbol set (s1, . . . , sk) and using a transformation of a matrix to determine the parity check bits. The first N2 columns of the matrix is defined that for column i, 1≦i≦└m/2┘, a value of 1 is assigned to row position i and a value of 1 is assigned to row position i+└m/2┘, all other row positions have a value of 0. Additionally for column i, └m/2┘+1≦i≦N2<m , a value of 1 is assigned to row position i−└m/2┘ and a value of 1 is assigned to row position i+1, all other row positions have a value of 0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.