Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination
US6785870B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Jan 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing speed and power consumption of an integrated circuit having at least one path having at least one gate involves creating a parent state representing a partition of the integrated circuit design. Each device in the parent state further has associated device size information and device type information. A population of individual states are created from at least one parent states. These individual states are scored for timing and power dissipation. Survivor individual states of the population are determined based upon scores of each state of the population. The steps of creating the population of individual states, scoring states, and determining survivor states, are iterated as needed. Survivor states are then further optimized with a greedy search, and a best individual survivor state is selected as an optimized state of each partition. The integrated circuit netlist is adjusted to correspond to the optimized state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.