Patent · US Expired

Test structures for simultaneous switching output (SSO) analysis

US6788098B1 · kind B1 · utility

10Cited by

2References

20Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Alaa A. Alani · Uxbridge, GB
Johann Leyrer · Munich, DE
Human Boluki · Munich, DE

Key dates

Filing date	Apr 16, 2003
Grant date	Sep 7, 2004
Priority date	—
Expiry date	Apr 16, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/14
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The a third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.