Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude
US6788579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | May 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.