System and method for processing data in a memory array
US6788585B1 · kind B1 · utility
2Cited by
8References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processing data is provided that includes receiving a first request in a first clock cycle from a processor for access to a first data segment corresponding to a first address included in the first request. A second request for access to a second data segment corresponding to a second address included in the second request is received during a second clock cycle. The second data segment is disabled from being communicated to the processor and the first data segment is communicated to the processor in response to the second request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.