Instruction address generation and tracking in a pipelined processor
US6789184B1 · kind B1 · utility
3Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Aug 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30149
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each instruction at each stage. The address pipeline may include program count (PC) generation logic to automatically calculate the PC of the next instruction based on the width of the current instruction for sequential program flow. The address pipeline may also track valid bits associated with each instruction and store the address of the oldest valid instruction for return to the original program flow after a disruptive event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.