Method and apparatus for automatic layout of circuit structures
US6789246B1 · kind B1 · utility
205Cited by
8References
67Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2002 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that involves retrieving a generic layout description of a circuit structure from a first database that stores a plurality of generic layout descriptions. The method also involves retrieving a foundry design rule profile of a semiconductor manufacturing process from a second database that stores a plurality of semiconductor manufacturing process design rule profiles. The method also involves automatically generating a layout of the circuit structure that conforms to the foundry design rule
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.