Analog hold cell in a CMOS process
US6791374B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jul 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hold cell implementing a closed-loop, common mode negative feedback method is provided. The hold cell enables generation of an accurate constant output voltage regardless of temperature-dependent leakage currents associated with parasitic diodes and non-ideal devices. The accurate constant output voltage provided by the hold cell is used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal is used to maintain long-term timing accuracy in host devices during sleep modes of operation. Incorporation of the hold cell in a low power oscillator is fully implementable in a CMOS process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.