Low jitter high phase resolution PLL-based timing recovery system
US6791379B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.