Digital video processing
US6791552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1999 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jul 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Digital video processing apparatus comprising: a plurality of render processors arranged in an operational sequence, each operable to render an output result relating to an image of a video signal from input data relating to that and/or other images received from a preceding render processor in the operational sequence; and a render controller for controlling rendering operation of the render processors; each render processor being operable to communicate dependency data to the render controller, indicating which images must be rendered by a preceding render processor in order for that render processor to render output data relating to a required image; and the render controller being operable to control operation of the render processors so that images required by each render processor are rendered by preceding render processors in the operational sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.