Two-dimensional buffer pages using bit-field addressing
US6791557B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Nov 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0132
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations. In one implementation, a buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; at least one memory device, each memory device having a plurality of memory pages including a plurality of memory locations, each memory location having an address; and where each data element corresponds to an entry in one of a plurality of buffer pages, where each buffer page has a plurality of entries along a first dimension corresponding to the first order and a plurality of entries along a second dimension corresponding to the second order, where data elements are stored according to the first order using blocks of buffer pages, each block having a number of buffer pages equal to a power of 2, where data elements are stored to the memory device in the first order and retrieved from the memory device in the second order, and where at least one memory page stores data elements in multiple locations according to the first order and stores data elements in multiple locations according to the second order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.