Dual ported memory for digital image sensor
US6791611B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 2001 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0068
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory is disclosed. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.