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US6791776B2 · kind B2 · utility
10Cited by
6References
8Claims
0Family size
Assignees
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Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/09
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.