Double data rate memory interface
US6791889B2 · kind B2 · utility
17Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring stored data from the memory device to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.