Maintaining synchronization over asynchronous interface
US6791987B1 · kind B1 · utility
6Cited by
12References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1998 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Oct 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/407
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There is no common clock between two system over an asynchronous interface, such as an asynchronous network or bus. The rate of data transmission of constant bit rate data from one system can be considered constant when averaged over time. A receive system can synchronize its system clock by using timing information derived by counting received packets over a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.