System apparatus and method for storage device controller-based message passing having effective data channel bandwidth and controller cache memory increase
US6792505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2001 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jun 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first memory controller and a first cache coupled to the first memory controller, the first memory controller including first interface for coupling with second auxiliary processor including second memory controller and associated second cache and second interface for coupling with first auxiliary processor, first memory controller including logic for treating the caches as single memory; a bus coupling first primary processor and first auxiliary processor; and interconnection channel separate from the bus coupling first interface of first memory controlled and second interface of second memory controller. Interconnection may be an out-of-band channel permitting device-to-device sharing of associated cache memories without requiring data transfer over the bus. Method and computer program product are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.