Memory architecture for a high throughput storage processor
US6792506B2 · kind B2 · utility
13Cited by
8References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2002 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Jul 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. User memory may pass through memory in a single hop by combining parity generation with FIFO buffering in the read and write user data paths. Independent memory channels may be controlled to level the load providing high memory bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.