System for addressing processors connected to a peripheral bus
US6792515B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | Nov 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combination of data processing systems that are connected to a common peripheral bus, such as a PCI bus. The processor(s) of each system or blade may communicate with the peripheral bus through an intermediate bus controller. The bus controller may include facilities, such as registers that define a starting address, suitable for defining a window in the blade's system memory that is available or visible to other processors (or masters) on the bus. One or more of the bus controllers may be configured to read information that uniquely identifies each system or blade. The bus controller may use this identification information to define the window in the blade's system memory that is visible to other processors. In an embodiment where each blade is connected to a PCI bus through a CompactPCI® connector, the identification information may be read from the geographic address (GA) pins on the system's J2 connector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.