Reliable hardware support for the use of formal languages in high assurance systems
US6792560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2000 |
| Grant date | Sep 14, 2004 |
| Priority date | — |
| Expiry date | May 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0721
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dataflow processor comprising a combiner for combining instructions and data, processing elements for carrying out the instructions, has error checking at the inputs to the processing elements and the combiner, and has self-checking circuitry for these parts. The amount of circuitry which needs to be trusted, (i.e. of proven design, and verified operation) can be advantageously limited. This enables the processor to be constructed more simply and to operate faster. The processing elements may have a series of state machines, each checking the output of the previous. Self checking circuitry may be constructed using combinations of basic configurable verified circuit. This circuit has a reversible Boolean function, and other circuitry to check its output. The other circuitry has a second reversible Boolean function for regenerating the original inputs, and a comparator for verifying if the regenerated values match the original values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.