Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features
US6794691B2 · kind B2 · utility
2Cited by
8References
53Claims
0Family size
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Inventor
Key dates
| Filing date | Jan 21, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jan 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.