Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same
US6794729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jun 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10719
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.