Pad circuit and method for automatically adjusting gain for the same
US6794893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Apr 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit therein. The pad circuit includes an input/output pin, a gain-adjustable output buffer, an input buffer and a signal feature detector. The method includes the steps as follows. A test signal is firstly issued from the core logic circuit to the gain-adjustable output buffer, while the test signal is then manipulated and outputted to an external device via the input/output pin. Next, a feedback test signal is fed into the input buffer from the external device, while a test result is realized according to a waveform feature of the feedback test signal. Finally, the gain of the gain-adjustable output buffer is adjusted according to the obtained test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.