Delay locked loop with digital to phase converter compensation
US6794913B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit 300 consistent with certain embodiments of the present invention has a delay line 304 with coarse adjustment 322 and fine adjustment 360 inputs. The coarse adjustment input 322 provides an overall adjustment of all of the delay line's delay elements while the fine adjustment inputs 360 permit adjusting the individual delay value of each delay element. A first multiplexer 330 receives the delay tap outputs and produces a first selected output while a second multiplexer 334 also receives the delay tap outputs and produces a second selected output. A measurement circuit 344 measures a difference between the first and second output as a measurement of a selected delay element's delay value. An error calculator 346 receives the output of the measurement circuit and calculates fine adjustment voltages for each of the selected delay elements. A tuning circuit 350 applies the fine adjustment voltages to the fine adjustment inputs of the delay line 304.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.