MOS latch with three stable operating points
US6794915B2 · kind B2 · utility
5Cited by
6References
2Claims
0Family size
Inventors
Key dates
| Filing date | Nov 5, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Nov 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3568
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A tristable latch circuit fabricated utilizing standard MOS process technology includes a biasing element for identically biasing the MOS transistors in triode (as opposed to saturation) to implement a third stable operating point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.