Clamp circuit
US6794921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.