Frequency acquisition for data recovery loops
US6794946B2 · kind B2 · utility
Inventor
Key dates
| Filing date | May 22, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jun 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency monitor includes an edge detector which produces a pulse for each rising or falling edge of an error signal. The error signal itself has a frequency that is responsive to a difference between frequencies of two input signals. A switched capacitor circuit has an effective average resistance that depends on the rate or frequency of the edge detector output pulses. A capacitor holds a charge that depends on the effective average resistance of the resistive circuit. Finally, comparator produces an output based on the charge held by the capacitor. The comparator output indicates whether the difference between the two input signal frequencies is less than some predetermined amount. A selector, responsive to the comparator, selects from a data phase detector circuit and a frequency acquisition circuit to control an oscillator. The oscillator produces a clock signal at a sampling frequency, which is used by the detector circuit to receive data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.