Programmable converter having an automatic channel sequencing mode
US6795000B1 · kind B1 · utility
3Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.