Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
US6795003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Feb 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.