ATM buffer system
US6795396B1 · kind B1 · utility
3Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2000 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | May 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An ATM buffer system includes a buffer to communicate with 16 ATM ports, and the system can implement two buffers to communicate over 32 ATM ports. A flow control signal is provided between the buffers in the 32-port configuration to route a buffer status signal to an ATM matrix using overhead data. The multiple buffers communicate with the ATM matrix using a single low voltage differential signal (LVDS) transmit and receive connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.