Programmable synchronization structure with auxiliary data link
US6795451B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2000 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Mar 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0066
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is provided for creating an auxiliary link embedded in the overhead structure of a primary data link. The primary data link is organized in a frame structure which includes data sections and header sections. Information in the header sections is used to synchronize and capture transmitted messages. However, not all the overhead bits need be used for synchronization. Bits may be selectively “robbed” from the header section and used to transfer information in an auxiliary data link. The number of bits that are used to support the auxiliary data link, as well as the placement of these bits in the header section are both selectable. An apparatus, specifically the AMCC 3062 Performance Monitor IC, has also been described which supports the establishment of an auxiliary data link in accordance with the above-mentioned method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.