Integrated data clock extractor
US6795514B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Mar 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for extracting a data clock signal from an input data stream, comprising a programmable delay element for receiving an arbitrary clock signal, delaying the arbitrary clock signal by a variable programmable amount and in response generating an extracted data clock signal, and a clock phase detector for comparing logic level transitions of the input data stream with transitions of the extracted data clock signal and in response generating a delay adjust signal for defining the variable programmable amount of delay such that the transitions of the input data stream are substantially aligned with the transitions of the arbitrary clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.