Selective memory controller access path for directory caching
US6795897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2002 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Oct 21, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99942
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system and corresponding method for supporting a compressed main memory includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register; where the corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memory line corresponding to the cache line being written, writing the content of the cache line into the appropriate position in the memory line, compressing the data contained in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.