Microprocessor with selected partitions disabled during block repeat
US6795930B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2000 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | May 5, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.