Multiple traps after faulty access to a resource
US6795937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide efficient resource access control in a computer system, a trap handler for handling a trap in the event of a faulty resource access being detected is arranged to define a diversion for subsequent access attempts to the same resource. An address translation mechanism is responsive to indication of a diversion for a resource access to modify an address mapping, whereby subsequent attempts to access the resource are diverted in accordance with the diversion. The trap handler can be arranged in a conventional manner to process an exception of the first faulty access to the resource. However, by defining the diversion, which can be used to map further attempts to access the same resource, unnecessary exception processing can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.