Method of manufacturing a semiconductor device
US6797615B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, in which a surface (1) of a semiconductor body (2) is provided with a first metallization layer comprising conductor tracks (3, 4), among which a number having a width w an a number having a greater width. On this structure an insulating layer (5) is deposited by means of a process in which the thickness of the formed insulating layer (5) is dependent on the width of the subjacent conductor tracks (3, 4), after which a capping layer (6) is deposited on the insulating layer (5). Then the silicon oxide layer is planarized by means of a polishing process. In this method, the conductor tracks having a width greater than w are split up into a number of parallel strips (10) having a width w, which strips are locally connected to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.