Circuit for asynchronous reset in current mode logic circuits
US6798249B2 · kind B2 · utility
5Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.