Method and apparatus for providing multiple clock signals on a chip using a second PLL library circuit connected to a buffered reference clock output of a first PLL library circuit
US6798257B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Sep 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for providing multiple clock signals on a chip using a second phase-locked loop library circuit connected to a buffered reference clock output of a first PLL library circuit which may be used, inter alia, in a computer or communications system, such as a computer or communications device, packet switching system, router, other device, or component thereof. Known prior circuits would typically use multiple off-chip reference clock signals for those applications that require multiple reference clocks. Implementations according to the invention may be particularly useful for possibly providing a lower-cost solution when, for example, such a circuit provides the capability to maintain tight timing, without sacrificing input pins, or excessively loading the PC board's clock driver. Various implementations of such circuits include an ASIC or those using any chip implementation technology or combinations of technologies, including but not limited to VLSI design and discrete components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.