Reset feature for a low voltage differential latch
US6798263B1 · kind B1 · utility
5Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Nov 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential latch circuit with a differential reset function includes a first arrangement of transistors configured to perform a latch function and a second arrangement of transistors, connected to the first arrangement of transistors, configured to perform a reset function. The first arrangement of transistors includes branches having three cascoded transistors, and the second arrangement of transistors includes branches having two cascoded transistors. This configuration enables the latch circuit to use lower power supply voltages relative to conventional latch circuits that require four more cascoded transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.